JTAG Connectors and Interfaces: An Overview

The standard hardware tool for testing, programming, and debugging embedded systems is known as JTAG. Developed by the Joint Test Action Group, it's available in most microcontrollers and FPGAs. Anyone who has recently programmed a modern microcontroller has likely used JTAG or a related standard.

Here's a look at what this standard is and why it's essential for testing.

Evolution of JTAG

JTAG emerged in the 1980s as a solution to account for increasing IO pin density and the use of ball-grid-array (BGA) packaging. The standard called for introducing a small logic cell for boundary scan to improve test functionality while a test access port (TAP) executes commands. It's a flexible system that allows manufacturers to add commands and logic blocks that facilitate programming and debugging.

One of the reasons for the widespread adoption of JTAG for device programming is that it allows for implementing custom logic. Binary coding for addresses lowered the pin count, opening the door to larger memory. Then serial protocols gave programmers access to devices through a few pins regardless of memory size. Interface standardization led to uniformity across devices with different types of implementation.

The standard has been extended with tools such as ARM's Serial Wire Debug (SWD), allowing JTAG to be more diverse. In order to meet JTAG compliance in today’s world, devices must use the following types of pins: text data input (TDI), test data output (TDO), test clock (TCK), and test mode select (TMS).

Testers use a state machine, which is a behavioral model regarding changing states through inputs. The testing state machine exists within a test access point (TAP) controller, which interprets TCK and TMS signals. The two different modes of the state machine are for instruction and data. A state machine may also have an optional test reset pin (TRST).

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JTAG Features

JTAG is a boundary-scan system that tests hardware interconnects between multiple ICs. The JTAG system involves reading connector pin values for testing functionality.

Only four or five pins are necessary to operate a JTAG TAP, which communicates with a JTAG interface device. While there is no standard connector for JTAG, it must be a standard male header such as ARM JTAG 20, ARM JTAG 14, and TI JTAG 14. The ARM JTAG 20 can be substituted with the similar Segger J-Link and J-Trace connectors.

Other headers that may be considered are the STMicroelectronics STDC14, the Infineon OCDS 16-pin header, the CoreSight 10, and the CoreSight 20. Most headers are typically male with 10-20 pins and a pin pitch of .05 to .1 inches.

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